Embodiments of the present invention disclosed herein relate to techniques of voltage generation in semiconductor memory apparatuses and more particularly, to a voltage generator capable of reducing current consumption by minimizing the number of pumping cycles under the condition of low power.
Most memory chips accessing memory cells usually conduct refresh operations by selecting word lines or rows by means of row addresses. Especially, in a DRAM as a kind of volatile memory, as memory cells must be operable during long refresh times, cell transistors have high threshold voltages. Thus, an elevated voltage (VPP) is required for turning such memory cells on, and for reading/writing data from/to the memory cells.
Since the level of the elevated voltage (VPP) is higher than or equal to an external power source voltage (VDD), a semiconductor memory apparatus usually makes the elevated voltage (VPP) by conducting an internal pumping operation. A circuit for generating the elevated voltage (VPP) by a pumping operation is referred to as an elevated generator (or pumping voltage generator).
With regard-to generation of the elevated voltage (VPP), FIG. 1 shows a circuit diagram of a conventional voltage generator.
The conventional voltage generator is formed by a reference voltage generator 10, a pumping voltage detecting section 20, and a pumping section 30.
The reference voltage generator 10 outputs a reference voltage Vrefp to the pumping voltage detecting section 20. The pumping voltage detecting section 20 outputs a pumping enable signal PPEN to the pumping section 30 after detecting the level of a pumping voltage VPP in accordance with the reference voltage Vrefp. The pumping section 30 generates the pumping voltage VPP by conducting a pumping operation in accordance with the pumping enable signal PPEN. The pumping voltage VPP is applied to a selection line of a memory cell 40, i.e., a word line, to read/write data. A capacitor C1 is coupled between a terminal of the pumping voltage VPP and a ground voltage terminal.
FIG. 2 is a circuit diagram of the pumping voltage detecting section 20 shown in FIG. 1.
The pumping voltage detector 20 includes a pumping voltage dividing section 21 and a pumping enable signal generating section 22. The pumping voltage dividing section 21 is configured to divide the pumping voltage VPP by means of resistors R1˜R6 serially coupled between the pumping voltage terminal and the ground voltage terminal, generating a divisional voltage DIV_VPP.
The pumping enable signal generating section 22 includes a comparing unit formed by PMOS transistors P1 and P2 and NMOS transistors N1˜N6, and a driving unit formed by PMOS transistors P3˜P5 and NMOS transistors N7˜N9.
The comparing unit outputs a result arising from comparing the divisional voltage DIV_VPP with the reference voltage Vrefp. The driving unit outputs the pumping enable signal PPEN by driving the result output from the comparing unit.
The divisional voltage DIV_VPP is based on of the reference voltage Vrefp. Namely, the pumping voltage detecting section 20 outputs the pumping enable signal PPEN at low level when the divisional voltage DIV_VPP is higher than the reference voltage Vrefp. But, when the divisional voltage DIV_VPP is lower than the reference voltage Vrefp, the pumping enable signal PPEN goes to high level to make the pumping section 30 conduct the pumping operation.
As the pumping voltage VPP is involved in accessing memory cells along a row, it causes large current consumption when the memory cell 40 is operating in a row access mode or a refresh mode.
In detail, the amount of current IPP consumed by a current source CC1 during the row access mode is proportional to the level the pumping voltage VPP decreases. Thus, as the pumping voltage VPP drops under a target value, the pumping enable signal PPEN is activated to make the pumping section 30 operable. The pumping section 30 boosts an external power source voltage VDD to double or triple its level.
The following Table 1 simply shows a comparison of current efficiencies and pump structures by voltage products.
TABLE 1ProductPump structureCurrent efficiency (IPP/IDD)1.8 VTrippler40~50%2.5 VDoubler25~35%3.3 VDoubler25~35%
As can be seen from Table 1, when the target level of the pumping voltage VPP is 3.3˜3.5V, the pump structure of a product using a 2.5V external is that of a doubler. And, a product using a 1.8V external power source voltage uses a trippler pump structure. Here, if a doubler pump structure is used in a product with a 1.8V external power source voltage, an ideal voltage 3.6V is logically generated, but this is very difficult in practice.
Further, an internal elevated voltage should be constant even with variation of the external power source voltage VDD (permitted to be 10% higher or lower). Therefore, although the external power source voltage VDD approximates the pumping voltage, a doubler pump structure is required.
For instance, even when the external power source voltage VDD is 3.3V and the pumping voltage VPP is 3.3V, the external power source voltage VDD may be supplied externally by 3.0V level and hence there is a need for a doubler pump structure. Also, a pump structure boosting VDD up to 1.5 times, instead of the doubler pump structure, may be considered, but there is difficulty in implementing the circuit architecture. Even with the doubler pump structure, the current of IDD flowing therein unavoidably makes the IPP current output less than 50% efficient. In an ideal doubler pump structure, the external power source voltage VDD must have a current of 2 mA in order to generate the pumping voltage VPP at 1 mA.
On the other hand, trippler pump structures are also employed in semiconductor memory products using lower voltages. The pump structure for 2.5V or 3.3V is constructed in a single chip for the purpose of enhancing the mediocrity of the product. In this organization, a trippler pump structure operating over a wide range of 1.8˜3.3V is designed so it may be changed into a doubler pump structure when there is a need to use 2.5V or 3.3V.
FIG. 3 shows the results of a simulation that represents the efficiency of a pump using an external power source voltage over a wide range. The graph of FIG. 3 depicts the pumping efficiency when boosting the external power source voltage VDD up towards the target level of the pumping voltage VPP of 3.3V. It can be seen from FIG. 3 that the pumping efficiency is just over 30% when a pumping operation is carried out by a doubler structure and there is a need for using an IDD current over three times the desired IPP current. Thus, it causes an IDD current loss of about 70% using a pumping operation with a doubler structure at 3.3V.
In particular, as DRAM memories are employed in mobile storage apparatuses requiring low power, such current losses would create malfunctions of operating voltages.